mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 55

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Delay Adjust[11:0]
Initialization Lead
2’s complement
Field
SPR
[7:1]
ADJ
SM
SE
A
B
I
Table 22 - CPS-Packet Disassembly Structure (PCM/ADPCM) Fields (continued)
Name of Field
Structure
Initialized bit
Initialisation
Lead
Slip Mode
Slip Error
Report Enable
Delay
Adjustment
pending
2’s
Complement
Delay Adjust
Silence
Suppression
Enable
Clock recovery
reference A
Clock recovery
reference B
Byte Address
Offset/Bits
+6/b15:b14
+4/b14:b8
+6/b11:b0
+4/b15
+6/b13
+6/b12
+8/b14
+8/b13
+8/b12
Zarlink Semiconductor Inc.
Used
MT90502
55
Structure initialized by hardware bit. Written to ‘0’ by
software upon opening the channel, written to ‘1’ by
hardware upon receiving the first CPS-Packet.
Delay in frames that the first byte of the first
CPS-Packet will go through before being sent on the
TDM bus. This can be set to a lower value in order
to minimise delay or to a higher value to avoid slips
during the first CPS-Packets of the connection. Its
value cannot exceed the Max PDV field. Typically,
this field would be set to (Max PDV)/2 when
initializing in the middle, or to 1 or 2 when initializing
close to the edge.
Action to be taken upon a slip.
‘0x’ = Slip to edge of circular buffer on underruns
‘1x’ = Slip to middle of circular buffer on underruns
‘x0’ = Slip to edge of circular buffer on overruns
‘x1’ = Slip to middle of circular buffer on overruns
When ‘0’, underrun and overrun slips will not be
reported. When ‘1’, they will be reported.
Written to ‘1’ by software when a delay adjustment
must be done by the hardware. Hardware will clear
this field once the delay adjustment has been
performed.
Two’s complement number that will be added to the
write pointer when the next CPS-Packet arrives. A
value of 0 will not modify the delay. A value of -1 will
reduce the delay by one frame. A value of +1 will
increase the delay by one frame. Any time an
adjustment is performed the Lowest and Highest
delay fields will be adjusted accordingly.
When ‘1’, any byte matching the “silent_pattern”
(contained in register 0410h) will not be written to
the external memory, causing silent padding to be
inserted instead.
When ‘1’, a pulse will be sent to the clock recovery
module indicating that a reference packet (a timing
CPS-Packet) has been received. This bit
corresponds to clock recovery channel A which is
independent of clock recovery channel B.
When ‘1’ a pulse will be sent to the clock recovery
module indicating that a reference packet (a timing
CPS-Packet) has been received. This bit
corresponds to clock recovery channel B which is
independent of clock recovery channel A.
Description of Field
Data Sheet