mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 68

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.5.4
The RX TDM supports compression on PCM/ADPCM channels at the following data rates: 40, 32, 24 and 16 kbps.
Each frame maintains a 5-, 4-, 3- or 2-bit compressed value in the high or low bits of the TDM byte and the
remainder indicates the data rate (see Figure 7 on page 32 and Figure 10 on page 35).
2.5.5
When processing HDLC channels on a per frame basis, the TDM RX Module will transmit either data bytes or
HDLC null patterns (All 1s in bit-wise HDLC or 7Eh in byte-wise HDLC). See Section 2.10, HDLC on page 101.
HDLC null patterns are transmitted between HDLC packets. The RX SAR communicates packet information to the
RX TDM through a packet descriptor queue held in external memory. A maximum of 16 descriptors per channel
may be retained in external memory. The descriptor contains the origin channel number of the AAL2 channel, base
address, and length of the CPS-Packet within the buffer.
Fields in Italic are used by Hardware only.
Fields in Plain are written to by the CPU/Software.
+FFCh
+FF4h
+FF8h
+000h
+004h
+008h
Compression
HDLC
Figure 32 - CPS-Packet Descriptor Queue Pointers Structure (HDLC Streams)
CPSPDQ Stream 1021
CPSPDQ Stream 1022
CPSPDQ Stream 1023
CPSPDQ Stream 0
CPSPDQ Stream 1
CPSPDQ Stream 2
CPSPDQ Pointers
Zarlink Semiconductor Inc.
MT90502
+2
+0
CPSPDQ Length: Initialized to the number of timeslots in the HDLC stream.
CPSPDQ WP and RP: Pointers to the CPS-Packet Descriptor Queue.
CPSPDQ structures are located in RX SSRAM Memory. Address range for
structures is +7000h to +071FCh, +0E000h to +0E3FCh, +0C000h to
+1C7FCh and +38000h to +38FFCh for 128, 256, 512, and 1023 channels
respectively.
Each structure is 4 bytes in size.
b15
CPSPDQ Len[3:0]
CPSPDQ Len[7:4]
68
b14
b13
b12
b11
b10
CPSPDQ WP[11:0]
CPSPDQ RP[11:0]
b9
b8
b7
b6
b5
b4
b3
Data Sheet
b2
b1
b0