mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 58

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

HDLC Stream
Address[15:0]
Read Pointer
Write Pointer
Number [9:0]
Control Byte
Circ. Buffer
Circ. Buffer
HDLC
Field
CRC
SUE
[9:1]
[9:1]
[7:0]
LE
H
A
B
I
Name of Field
Clock recovery
Clock recovery
Address [15:0]
Report Enable
Circular Buffer
Circular Buffer
HDLC Stream
HDLC Control
Read Pointer
Header Type
Write Pointer
CRC enable
Initialized bit
Table 23 - CPS-Packet Disassembly Structure (HDLC format) Fields
reference A
reference B
Loss Error
Send UUI
Structure
Number
enable
HDLC
Byte
Offset/Bits
+0/b14:b12
+6/b15:b0
Address
+0/b8:b0
+2/b8:b0
+4/b9:b0
+8/b7:b0
+0/b11
+0/b10
+8/b13
+8/b12
+0/b9
+8/b8
Used
Byte
Zarlink Semiconductor Inc.
MT90502
Gives the format of the HDLC header
‘000’ = no header bytes
‘001’ = one byte address
‘010’ = two byte address
‘011’ = one byte address + control
‘100’ = two byte address + control
others = reserved
Indicates if a 16-bit trailing CRC is to be appended to the
CPS-Packet.
This bit must be set in order for CPS-Packet loss errors (e.g.
losses due to silence suppression or to network quality) to
be reported on this CID. CPS-Packet loss errors are
detected by circular buffer overflow, or due to CPS-Packet
descriptor queue overrun (in HDLC), and by sequence
number errors (in PCM).
Reset by software upon opening the channel, set by
hardware upon receiving the first CPS-Packet.
Points to the location in the circular buffer used to contain
HDLC packets where the next CPS-Packet will be written.
Points to the location in the circular buffer used to contain
HDLC packets where the next byte is to be read to be sent
on the TDM bus
Pointer to beginning of the HDLC Stream structure in the
RX_TDM control memory to which this channel must be
routed. Directing many HDLC streams to the same HDLC
Stream structure allows many HDLC channels to point to a
single stream.
Address used to form the HDLC header. This field is ignored
if the Header Type is ‘000’
When ‘1’, a pulse will be sent to the clock recovery module
indicating that a reference packet (a timing CPS-Packet) has
been received. This bit corresponds to clock recovery
channel A which is independent of clock recovery channel B.
When ‘1’, a pulse will be sent to the clock recovery module
indicating that a reference packet (a timing CPS-Packet) has
been received. This bit corresponds to clock recovery
channel B which is independent of clock recovery channel A.
Send UUI in control byte enable. When set and when
Header Type is ‘011’ or ‘100’, the 5 MSBs of the HDLC
control byte will be the UUI.
Control byte used to form the HDLC control byte. This field is
ignored if the Header Type is not ‘011’ or ‘100’.
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Description of Field
Data Sheet