mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 166

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 710h
Label: adapa0
Reset Value: 0001h
Adapa_clk_divisor_reset
Adapa_source
adapa_clk_divisor_load_now
Reserved
Address: 712h
Label: adapa1
Reset Value: 0002h
adapa_div_integer
Address: 714h
Label: adapa2
Reset Value: 0000h
Adapa_div_fraction
Label
Label
Label
Position
Bit Position Type
Bit Position Type
15:14
12:11
Table 167 - Adaptive Module A Register 0
Bit
Table 168 - Adaptive Module A Register 1
Table 169 - Adaptive Module A Register 2
10
13
15:0
15:0
Type
PUL When written to '1', this will allow the new div_integer and
PUL Reserved. Always read as “00”
RW When '0', this will force the Adaptive module A's clock divisor to
RW “00” = clkrecov_pulse_a; “01” = gpio[0] (any change); “10” =
RW Adaptive module A's mem_clk divisor (fractional part). Range 0
Zarlink Semiconductor Inc.
RW Adaptive module A's mem_clk divisor (integer part). Range 2
reset.
gpio[0] (rising edge); “11” = gpio[0] (falling edge).
div_fraction to be used.
MT90502
to FFFFh.
to FFFFh.
166
Description
Description
Description
Data Sheet