mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 54

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Circ. Buffer Write
Pointer [23:0]
Max PDV (in
frames) [9:0]
Field
HDLC/xxPCM CPS-Packet Disassebly Structure Space
+7FA0h
+7FC0h
+7FE0h
+0000h
+0020h
+0040h
+0060h
+0080h
CPS-Packet Disassembly structures located in RX SSRAM memory. Address
range of strucutres is +6000h to +6FE0h, +C000h to +DFE0h, +18000h to
+1BFE0h and +30000h to +37FE0h for 128, 256, 512 and 1023 channels
respectively.
Index of structure is given by CPS-Packet Disassembly Structure Number
(+00h [b9:b0]) in CID Descriptor Structure.
Each structure is 32-bytes in size.
LC
LE
C
CPS-Packet Dis. Struct. 1021
CPS-Packet Dis. Struct. 1022
CPS-Packet Dis. Struct. 1023
CPS-Packet Dis. Struct. 0
CPS-Packet Dis. Struct. 1
CPS-Packet Dis. Struct. 2
CPS-Packet Dis. Struct. 3
CPS-Packet Dis. Struct. 4
Table 22 - CPS-Packet Disassembly Structure (PCM/ADPCM) Fields
Name of Field
Compression
Ratio
CPS-Packet
Loss
Compensation
Enable
Loss Error
Report Enable
Max PDV (in
frames)
Circular buffer
write pointer
Figure 24 - CPS-Packet Disassembly Structure (PCM/ADPCM)
Byte Address
Offset/Bits
+0/b15:b13
+2/b15:b0,
+0/b9:b0
+4/b7:b0
+0/b11
+0/b10
Zarlink Semiconductor Inc.
Used
MT90502
54
+0h
+2h
+4h
+6h
+8h
+Ah
+Ch
+Eh
+10h
‘000’ = 64 kbps, ‘010’ = 40 kbps, ‘011’ = 24 kbps,
‘100’ = 16 kbps, ‘101’ = ADPCM auto-detect (can
change between 16, 24, 32 and 40 kbps), ‘110’ =
PCM & ADPCM auto-detect (can change between
16, 24, 32, 40, 64 kbps), others = reserved.
0: CPS-Packet Loss Compensation circuit disabled.
1: CPS-Packet Loss Compensation circuit enabled.
This bit must be set in order for CPS-Packet loss
errors (e.g. losses due to silence suppression or to
network quality) to be reported on this CID.
CPS-Packet loss errors are detected by circular
buffer overflow, or due to CPS-Packet descriptor
queue overrun (in HDLC), and by sequence number
errors (in PCM).
This indicates the maximum quantity of PDV that the
AAL2 Channel will incur. It is measured in frames
(i.e. 125 us). A value of 0 implies that there is no
PDV on the AAL2 Channel. The maximum value for
this field depends on the Number of EDUs and the
size of the RX Circular Buffers. It is defined as ((Size
of circular buffer) - 8*(Number of EDUs) -4) /2.
Pointer to the next memory location to be written
upon the arrival of the next CPS-Packet.
b15
Fields in Italic are used by Hardware only.
Fields in Plain are written to by the CPU/Software.
I
# of EDU
Last UUI[3:0]
SM
LI0
SPR
b14
C
Initialization Lead[7:1]
b13
SE
A
b12
ADJ
CPS-Packet Disassembly Structure (xxPCM)
B
Expected LI
b11
LC
Reserved
Circ. Buffer Write Pointer[15:0]
Highest Delay Encountered (in frames) [11:0]
Lowest Delay Encountered (in frames) [11:0]
CPS-Packet Counter[15:0]
b10
LE
SL
Description of Field
2’s complement Delay Adjust[11:0]
b9
TDM RP / First written byte Offset
b8
Max PDV (in frames) [9:0]
Circ. Buffer Write Pointer[23:16]
RL
b7
RU
b6
b5
b4
# Seq Bits / UUI M
b3
b2
b1
Data Sheet
b0