mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 24
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
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2.1.2.1
Extended Indirect Accessing solely employees the registers 000h to 00Ah to access the 68MB of addressable
memory space.
Synopsis: The access address is written to registers 000h, 008h, and 00Ah. The MT90502 will read/write to that
address and fetch/place the data value from/to register 004h. For all extended indirect accesses the CPU_A_DAS
bit will be held low.
Extended Indirect Writes
The following steps must be executed to perform an extended indirect write:
1. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value
write_enable
extended_parity
extended_data[15:0]
extended_a[32:20]
Reserved
extended_a[19:4]
holds true.
Field
Field
Extended Indirect Accessing
Field
13:12
15:14
15:0
Bit
15:0
Bit
12:0
15:13
Bit
Type
RW
RW
RW
Table 15 - Read/Write Data Register (004h)
RW
Table 16 - Address High Register (008h)
Table 17 - Address Low Register (00Ah)
Type
Table 14 - Control Register (000h)
RO
RW
Type
Reset
0000h
0h
0h
0000h
Zarlink Semiconductor Inc.
Reset
000h
0h
Active high write enables.
00 = read access.
01 = write to lower byte.
10 = write to upper byte.
11 = write to entire word.
This field is ignored for extended direct reads and all byte wide
extended direct accesses.
Read/Write Parity bits.
MT90502
Lower extended address [19:4]. In extended direct
addressing, bits 19:16 are employed for 16-bit data bus; bits
19:15 are employed or 8-bit data bus.
Reset
24
The extended indirect read/write data word register.
Invalid for extended direct access.
Upper extended address [32:20].
Description
Description
Description
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