mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 129

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 230h
Label: mem_parity0
Reset Value: 0000h
mema_parity_conf[1:0]
memb_parity_conf[1:0]
cpu_parity_conf
reserved
mem_parity_generation_data_mask
Address: 232h
Label: mem_parity1
Reset Value: 0000h
mem_parity_generation_add_mask[22:16]
reserved
Label
Label
Table 59 - Memory Parity Register 1
Table 58 - Memory Parity Register 0
Position
15:8
Bit
1:0
3:2
7:5
4
Zarlink Semiconductor Inc.
Position
Type
RW Selects how the parity bits of memory bank A are used
RW Selects how the parity bits of memory bank B are used
RW 1' = automatic parity calculation/checking on CPU
RW The data bits whose corresponding bit is set to '1' in this
RO Reserved. Always read as “00”
MT90502
15:7
6:0
Bit
(either as data bits or as parity bits). They should be set to
“11” to allow correct Underrun detection in the RX TDM
control memory. '0' = parity bits; '1' = user data.
(either as data bits or as parity bits). They should be set to
“11” to allow correct Underrun detection in the RX TDM
control memory. '0' = parity bits; '1' = user data.
accesses; '0' = CPU parity on CPU accesses (read and
writes).
vector will be used in parity calculation to the external
memory.
129
Type
RW The address bits whose corresponding bit is set
RW Reserved. Must always be “0000_0000_0”
to '1' in this vector will be used in parity
calculation to the external memory.
Description
Description
Data Sheet