mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 22

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Interrupt Initialization
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Interrupt Servicing
When interrupt2 is asserted (‘interrupt2’ pin):
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2.1.2
Set interrupt polarity, register interrupt2_conf[15:14].
Enable Interrupt2 for the CPU module by setting bit 0 in interrupt2_enable register (21Ah). The MT90502 will
generate an interrupt on interrupt2 according to the modules enabled in interrupt2_enable.
Set the individual CPU interrupt sources by enabling the respective bits in the ‘status0_ie’ register (104h).
Within the ‘status0_ie’ register there are two possible interrupt sources: internal_read_timeout_ie and
cpu_read_done_ie. In the MT90502 Register Description the interrupt bits are labelled IE (Interrupt Enable)
in the ‘Type’ column. This register offers the facility to mask/disable unwanted interrupts.
Read the interrupt flags to ascertain the module raising the interrupt. The CPU module interrupt flag is
located in register interrupt_flags (210h), this bit is named cpureg_interrupt_active.
If the cpureg_interrupt_active bit is set, locate the source of the CPU interrupt by reading the ‘status0’ at
102h, either internal_read_timeout and/or cpu_read_done.
To de-assert the interrupt the user must write a 1 to register 102h bits 3 and/or 4, internal_read_timeout and
cpu_read_done respectively. Only then will the interrupt be de-asserted.
000h
004h
008h
00Ah
Intel/Motorola Interface
Read/Write Data Register
Address High Register
Address Low Register
Control Register
The MT90502 CPU interface supports both Intel and Motorola modes
with an 8-bit or 16-bit data bus and multiplexed or non-multiplexed
address/data pins. The MT90502 supports 68 MB of addressable
space, therefore indirection addressing is necessary. The CPU
interface directly addresses four control words, delegated for
indirection accessing. The Indirection Register contents are shown in
Table 14 to Table 17 inclusively. The timing relationship pertaining to
the CPU Interface Registers and Extended Access is defined in
Section 4.3 on page 185.
Zarlink Semiconductor Inc.
MT90502
22
Data Sheet