mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 79

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

as a slave, has the choice of clocking on A, clocking on B, clocking on A with B as backup, or clocking on B with A
as backup. When set to perform automatic switch-over, the interface monitors the active bus master to determine if
its ct_c8 clock edges are within
upon the 1024 ct_c8 clock cycle. If ct_c8 or ct_frame errors are reported on the bus master signals, the ct_c8 or
ct_frame is considered invalid and the slave will switch to the backup master (if backup has been configured). The
MT90502 will always monitor these signals and will report errors on either of the two bus masters in status0 register
(702h).
2.7.5
When configured as a bus master, the MT90502 can be a bus master on A, B, backup on A or backup on B. The
difference between a bus master and a bus backup is that bus master drives all compatibility clocks, and the bus
backup does not. When configured as a bus backup, the MT90502 uses the same error signals or error flags to
determine if the current bus master is valid or if MT90502 reverts to be the master. Note that the bus mastership
can be overridden in registers mastership_hidden0 (774h), mastership_hidden1 776h) and mastership_hidden2
(778h) by ensuring that the MT90502 cannot drive the H.100/H.110 clock and frame signals. If the MT90502 is a
backup on the bus and the primary master fails, it will stop synchronising to the master and track the local
reference.
Once configured as bus master, MT90502 provides compatibility clocks generated by H.100/H.110 module.
Figure 42, “TDM Bus Timing - sclkx2 Generation,” on page 80 shows the MT90502’s compatibility signals
generated on H.100/H.110 interface.
Note: The fr_comp polarity in this drawing is always active low for simplicity. It can also be programmed active high.
fr_comp(8M,Strdl)
fr_comp(4M,Strdl)
fr_comp(2M,Strdl)
fr_comp(8M,First)
fr_comp(4M,First)
fr_comp(2M,First)
fr_comp(8M,Last)
fr_comp(4M,Last)
fr_comp(2M,Last)
Operating as a Master
ct_frame
ct_c8
Figure 41 - TDM Bus Timing - Fr_Comp Generation
±
35 ns of their expected edge times (122 ns apart) and the ct_frame signal occurs
Zarlink Semiconductor Inc.
MT90502
79
Data Sheet