mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 77

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.6.7
Due to the different possible configurations of the UTOPIA ports, the functions of some pins change, depending on
the configuration. The function of the CLAV (cell available) and ENB (enable data transfer) pins alternate when the
port is in ATM mode or PHY mode (see Figure 40, “External UTOPIA Interface,” on page 77). Please note that the
I/O direction of the pins remain fixed.
2.6.8
The UTOPIA module contains the ability to prevent cells in the 4-cell input FIFOs (RXA, RXB, RXC, TX Data Cell
FIFO and TX_SAR) from being processed by the UTOPIA module in case the output FIFOs (TXA, TXB, TXC and
RX_SAR) exceed programmable levels.
For each pair of input and output FIFO, a threshold can be set independently from 0 to 15 (for TXA, TXB and TXC
output FIFOs) or 0 to 63 (for RX_SAR output FIFO). Once the cell level in output FIFO exceeds that threshold, cells
from that input FIFO are blocked until the output FIFO empties itself below the threshold. There are cell arrival
counters and cell departure counters for each port.
2.7
2.7.1
The H.100/H.110 interface is compatible with the ECTF H.100/H.110 hardware compatibility specification,
Computer Telephony BUS (CT-BUS), and its implementation on the PCI computing platform. The TDM interface of
the MT90502 can be used to interface as bus master or bus slave with the H.100/H.110 bus. The MT90502
supports up to 32 TDM Streams running at 8.192 MHz (up to 4096 time slots). Also, as required in the specification,
16 TDM streams can be configured to run at lower frequencies of 4.096MHz or 2.024MHz. The MT90502 can
perform loopback on 128 channels.
PHY Device
H.100/H.110 Interface
External Interface Signals
UTOPIA Flow Control
Overview
rxclk
rxenb
rxclav
rxsoc
rxdata
rxpar
txclk
txenb
txclav
txsoc
txdata
txpar
Port A, B or C ATM Mode
MT90502 - ATM Mode
txa_clk (D12)
txa_enb (A13)
txa_clav (B13)
txa_soc (D14)
txa_d (C15 . . .)
txa_prty (D15)
rxa_clk (A9)
rxa_enb (B9)
rxa_clav (C9)
rxa_soc (C12)
rxa_d (A12 .. .)
rxa_prty (B12)
Figure 40 - External UTOPIA Interface
Zarlink Semiconductor Inc.
MT90502
77
ATM Device
rxclk
rxenb
rxclav
rxsoc
rxdata
rxpar
txclk
txenb
txclav
txsoc
txdata
txpar
Port A, B or C PHY mode
MT90502 - PHY Mode
txa_clk (D12)
txa_enb (B13)
txa_clav (A13)
txa_soc (D14)
txa_d (C15. . .)
txa_prty (D15)
rxa_clk (A9)
rxa_enb (C9)
rxa_clav (B9)
rxa_soc (C12)
rxa_d (A12. . .)
rxa_prty (B12)
Data Sheet