mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 128

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 22Ch
Label: rxc_clk_gen
Reset Value: 0403h
rxc_clk_div[5:0]
rxc_clk_divisor_load_now
rxc_clk_inv
rxc_clk_src[2:0]
rxc_clk_oe
rxc_clk_present
rxc_clk_divisor_reset
reserved
Label
Bit Position
15:14
10:8
5:0
12
13
11
6
7
Table 57 - Rx C Clock Division Register
Type
PUL
RW
RW
RW
RW
RW
RW
RW
Zarlink Semiconductor Inc.
MT90502
rxc_clk clock source division value. The rxc_clk clock source
(selected using rxc_clk_src) can be divided before being sent
out on UTOPIA. Note that odd values will force the duty cycle
to be maintained, rather than returning it to 50-50.
This bit, when written to '1', will force the new rxc_clk_div to be
applied immediately (possibly causing glitches on the rxc_clk).
This bit should only be set to one when loading the divisor
when the rxc_clk_present bit is cleared.
Note that it is possible to dynamically change the divisor value
without causing glitches on the output clock if this bit is not
written to 1.
When '1', the rxc_clk's source will be inverted before being
driven out on the rxc_clk pin.
“000”=txa_clk_in; “001”=txb_clk_in; “010”=txc_clk_in;
“011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in;
“110”=mem_clk; others = reserved.
rxc_clk output enable. Active high.
Set to '1' when the rxc_clk is present. If the user does not want
to use the txa UTOPIA interface, this bit should be left at '0'
regardless of the presence of the rxc_clk.
When '0', will reset the clock division.
Reserved. Must always be “00”
128
Description
Data Sheet