mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 139

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 462h
Label: aal0_timeout_period_low
Reset Value: 0000h
aal0_timeout_period[15:0]
Address: 464h
Label: error_timeout_period_high
Reset Value: 0000h
error_timeout_period[19:16]
reserved
Address: 466h
Label: error_timeout_period_low
Reset Value: 0000h
error_timeout_period[15:0]
Address: 468h
Label: pulse_register
Reset Value: 0000h
aal0_treated_pulse
error_treated_pulse
reserved
Label
Label
Label
Label
Bit Position
Table 89 - Error Timeout Period (High Word) Register
Table 88 - AAL0 Timeout Period (Low Word) Register
Table 90 - Error Timeout Period (Low Word) Register
Bit Position
Bit Position
15:2
Bit Position
0
1
15:0
15:0
15:4
Table 91 - AAL0 & Error Treated Register
3:0
Type
PUL
PUL
PUL
Type
RW
Type
Zarlink Semiconductor Inc.
Type
RW
RW
RW
When the AAL0 buffer has been treated, write this bit to '1' to
clear the alarm.
When the error buffer has been treated, write this bit to '1' to
clear the alarm.
Reserved. Always read as “0000_0000_0000_00”
MT90502
If an AAL0 cell remains in the buffer for the period in this
register or more, an alarm will be generated. In us.
This timeout period applies both to error reporting
structures as well as to CPU-destined CPS-Packets. In us.
139
This timeout period applies both to error reporting
structures as well as to CPU-destined CPS-Packets. In
us.
Reserved. Must always be “0000_0000_0000”
Description
Description
Description
Description
Data Sheet