mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 82

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

The mastership mode and slaveship mode of the MT90502’s TDM interface can be programmed using register
722h. Mastership mode determines on which bus(es), A or B, the MT90502 will act as a master or backup. When
configured as a master on a bus, the MT90502 drives the frame pulse and clock on that bus as well as the
compatibility signals (if enabled). When configured as a backup on a bus, the MT90502 drives the frame pulse and
clock on that bus, but does not drive the compatibility signals. The slaveship mode configures the MT90502 to
synchronize its internal timing to the ct_frame pulse and ct_c8 clock on either the A or the B bus. The slaveship
mode is completely independent of the mastership mode. An example configuration would have the mastership
mode set for the MT90502 to be a master on A and setting the slaveship mode for the MT90502 to track on A.
Register 774h can be used to override the operation of the MT90502 based on the selections made in register
722h. The automatic_master_override bit will enable the rest of the values in this register. The
mux0_select_override bit will stop the automatic fallback of the slaveship mode (from A to B or B to A). The
mux1_select_override bit will select between using ct_c8_a/ct_c8_b or H.110 PLL output clock as the feedback
signal to the H.110 PLL. The mux2_select_override bit will select between ct_c8_a/ct_c8_b or pll_clk as the
reference source for the H.110 PLL. The mux3_select_override bit will select between using either an external
pll_clk or the H.110 PLL output as the clock used to generate the ct_c8_x and ct_frame_x and clock signals.
Table 29 - H.100/H110 PLL Clock Selection Registers
automatic_master_override
mux0_select_override
mux1_select_override
mux2_select_override
mux3_select_override
pll_clk_in_frequency
ct_compatability_oe
ct_c8_frame_a_oe
ct_c8_frame_b_oe
mastership_mode
Figure 45 - H.100/H.110 PLL Clock Selection
slaveship_mode
Label
Zarlink Semiconductor Inc.
MT90502
82
Register
700h
720h
720h
720h
722h
722h
774h
774h
774h
774h
774h
Bit Position
1:0
1:0
3:2
5:4
0
1
2
0
1
2
3
Data Sheet