mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 140

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

3.5
Address: 500h
Label: control
Reset Value: 0000h
nibble_mode
hdlc_type
reserved
packaging_type
llman_process_enable
silent_bit_position
u_law_zero_illegal
reserved
test_status
Address: 502h
Label: status0
Reset Value: 0000h
llman_process_crashed
copying_out_of_bandwidth
frame_reading_out_of_bandwidth
bad_packet_length
circular_buffer_overflow
TX TDM Registers
Label
Label
Bit Position
14:9
7:5
15
0
1
2
3
4
8
Bit Position
Table 92 - TX TDM Control Register
Table 93 - TDM TX Status Register
0
1
2
3
4
Type
RW
RW
RW
RW
RW
RW
RW
RW
TS
Zarlink Semiconductor Inc.
0' = High bits used for ADPCM nibble, '1' = low bits used for
ADPCM nibble
HDLC framing method. '0'=Bit wise HDLC Framing; '1'=Byte
Wise HDLC Framing.
Reserved. Must be “0”.
0' = AAL2 header not present in HDLC data field; '1' = AAL2
header present in HDLC data field.
Enables the treatment of incoming TDM bytes from the H100
bus.
odd stream. “000” = bit 7, “111” = bit 0
When '1', 00h in u-law will be replaced by 02h before it is placed
on RX TDM bus.
Reserved. Must always be “0000_0000_00”
Reserved. Must always be “0”.
Indicates the position of the simple silence bit in the associated
MT90502
Type
ROL
ROL
ROL
ROL
ROL
140
Indicates that the linked-list manager crashed. This
indicates corrupt data in the linked list memory.
Data copying process between the H.100 interface
and the TX TDM was not fast enough. Indicates too
low an mem_clk speed for the amount of TDM
bandwidth.
Means that the frame reading process that reads from
the frame memory fell out of sync with the TDM bus.
This error will occur naturally at startup.
Received packet length on HDLC exceeded 64 bytes.
TX SAR did not read data fast enough from circular
buffer. Bad data integrity will ensue.
Description
Description
Data Sheet