mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 131

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 250h
Label: sdram_conf0
Reset Value: 0000h
sdrama_enable
sdramb_enable
sdrama_manual_access
sdramb_manual_access
sdrama_size
sdramb_size
sdram_refresh_freq
reserved
Address: 252h
Label: sdram_conf1
Reset Value: 0400h
sdram_refresh_cnt
Address: 254h
Label: sdram_conf2
Reset Value: 0200h
sdram_max_lateness
Label
Label
Label
Bit Position
Bit Position
Bit Position
Table 65 - SDRAM Configuration Register 2
Table 64 - SDRAM Configuration Register 1
Table 63 - SDRAM Configuration Register 0
15:0
15:8
15:0
7:6
0
1
2
3
4
5
Type
Type
PUL When written to 1 and sdrama_enable is '0', the values placed
PUL When written to 1 and sdramb_enable is '0', the values placed
Type
RW
RW
RW
RW
RW
RW
RW
RW Maximum number of refreshes that the SDRAM can be late
Zarlink Semiconductor Inc.
MT90502
Reserved. Must always be “0000_0000”.
Number of mem_clk cycles per refresh to the SDRAM.
When '0', the values placed in the sdram_conf3 register will be
placed on the SDRAM A pins.
When '0', the values placed in the sdram_conf3 register will be
placed on the SDRAM B pins.
in the sdram_conf4 register will be placed on the SDRAM A
pins.
in the sdram_conf4 register will be placed on the SDRAM B
pins.
0' = 4M x 16 (8 Megabytes), '1' = 8M x 16 (16 Megabytes)
0' = 4M x 16 (8 Megabytes), '1' = 8M x 16 (16 Megabytes)
“00” = 1 refresh every 16 cycles, “01” = 1 refresh every 8
cycles, “10” = 1 refresh every 4 cycles. Typical value “00”.
before reporting an error.
131
Description
Description
Description
Data Sheet