mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 193

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mt90502ag2

Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
t3_writes1 cpu_rdy_ndtack falling edge to write_access_active rising edge
t3_writes2 cpu_rdy_ndtack falling edge to cpu_d invalid
t1_muxed write_access_active falling edge to cpu_ale fall
t3_muxed cpu_rdy_ndtack falling edge to cpu_ale rising edge
t1_writes write_access_active falling edge to cpu_d valid
Symbol
t10
t15
t16
t17
t11
t5
t9
(when both CS, DS are low
Write Access Time
write_access_active falling edge to cpu_rdy_ndtack driven high
write_access_active rising edge to cpu_rdy_ndtack rising edge
cpu_rdy_ndtack rising edge to cpu_rdy_ndtack tri-state
cpu_ale high pulse width
cpu_d valid to cpu_ale falling edge
cpu_ale falling edge to cpu_d invalid
read_access_active
and R/W is high)
cpu_rdy_ndtack
Table 208 - Multiplexed CPU Interface - Motorola Mode - Write Access
cpu_d[15:0]
Figure 78 - Multiplexed CPU Interface - Motorola Mode - Read Access
cpu_ale
Description
t15
t1
Zarlink Semiconductor Inc.
t9
t16
MT90502
t17
t8
193
t5
t3_muxed
t14
t3_reads
Min. Typical
0
0
2
5
0
0
0
5
5
t12
t10
t11
2 * upclk - 4 ns
2 * upclk - 4 ns
Max.
740
12
10
8
Data Sheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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