mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 19

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

VSS (0 V): D9, D11, E5, E6, E9, E10, E13, E14, E17, E18, E21, E22, F4, F5, F22, H4, J5, J22, K5, K22, L4,
L11, L12, L13, L14, L15, L16, M4, M11, M12, M13, M14, M15, M16, N5, N11, N12, N13, N14, N15, N16, N22,
P5, P11, P12, P13, P14, P15, P16, P22, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, U5,
U22, V5, V22, AA5, AA22, AB5, AB6, AB9, AB10, AB13, AB14, AB17, AB18, AB21, AB22, AF25.
VDD3 (3.3 V): C3, C24, D23, E7, E8, E11, E12, E15, E16, E19, E20, G5, G22, H5, H22, L5, L22, M5, M22, R5,
R22, T5, T22, W5, W22, Y5, Y22, AB7, AB8, AB11, AB12, AB15, AB16, AB19, AB20, AC4, AC23, AD3, AD24,
AF1
Note: If MT90502 is only connected to 3.3 V devices on the H.100/H.110 bus, then 3.3 V can be connected to the
following pins. If any devices are 5 V then these pins must be connected to 5 V.
VDD5 (3.3 V or 5.0 V): B25, D24, H26, L26, P25, U24
AA23, T24, R26, N23,
AB2
AB3
AE2
AB1
AE1
Pin
A5
B5
AF26, AC24, AB23,
A26
D22
A25
C23
A23
Pin
AA1
M23
Pin
PLLGND1
PLLGND2
PLLGND3
PLLVDD1
PLLVDD2
PLLVDD3
pll_clk
Name
Name
tms
trst
tdo
tck
tdi
rst
I/O
Z
I
I/O
O
I
I
I
I
gpio[7:0]
Table 7 - Phase Lock Loop (PLL) Pins
Name
LVTTL (F)
reset
Table 10 - VDD5 (3.3 V or 5.0 V) Pins
Type
Table 5 - Miscellaneous Pins
Table 9 - VDD3 (3.3 V) Pins
Table 8 - VSS (0 V) Pins
LVTTL 6 mA (F)
Table 6 - JTAG Pins
Zarlink Semiconductor Inc.
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
I/O
I/O
I
MT90502
PLL reference clock used for H.100 Master clock generation
PLL Power Pin (3.3 V). Place one.01 uF, one 10 uF and one 100 pF
capacitor near PLL_VDD1 / PLL_GND1 pins.
PLL Power Pin (3.3V ). Place one.01 uF, one 10 uF and one 100 pF
capacitor near PLL_VDD2 / PLL_GND2 pins.
PLL Power Pin (3.3 V). Place one.01 uF, one 10 uF and one 100 pF
capacitor near PLL_VDD3 / PLL_GND3 pins.
PLL Ground Pin (0 V).
PLL Ground Pin (0 V).
PLL Ground Pin (0 V).
Type
LVTTL 6 mA
LVTTL (F)
19
Type
(F)
Global Hardware Reset (active low)
General Purpose I/Os
JTAG Test Reset
JTAG Test Clock
JTAG Test Data In
JTAG Test Mode Select
JTAG Test Data Out
Description
Description
Description
Data Sheet