mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 80

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

The sclk and sclkx2 signals can be programmed in mastership0 register (720h) to have identical or opposite
polarities as defined in the H.100/H.110 specifications. In addition, the frequency of sclk can be programmed to be
8.192 MHz, 4.096 MHz or 2.048 MHz.
The lower 16 streams on the H.100/H110 bus are grouped into 4 and are capable of operating at the following
frequencies: 8.192 MHz, 4.096 MHz, or 2.048 MHz. The MT90502 can be programmed such that all 32 streams
are arranged in groups of 4 streams - ct_c[3:0], ct_c[7:4], ct_c[11:8], ct_c[15:12], ct_c[19:16], ct_c23:20],
ct_c[27:24] and ct_c[31:28]. Each group can be assigned a desired frequency. These features are programmed in
clock_rates register (730h).
In addition, the MT90502, instead of supporting the full bandwidth of H.100/H.110, can be configured to only
interface with 4, 8 or 16 streams on the bus. This allows the MT90502 to operate at lower frequencies. The lowest
streams are used in these cases.
sclkx2(8M,inverted)
sclkx2(4M,inverted)
sclkx2(2M,inverted)
ct_frame
sclk(8M,inverted)
sclk(4M,inverted)
sclk(2M,inverted)
Figure 43 - TDM Bus Timing - Compatibility Clock Generation (other than sclk, sclkx2)
ct_c8
c16+
c16-
sclkx2(8M)
sclkx2(4M)
sclkx2(2M)
c2
c4
ct_frame
sclk(8M)
sclk(4M)
sclk(2M)
ct_c8
Figure 42 - TDM Bus Timing - sclkx2 Generation
Zarlink Semiconductor Inc.
MT90502
80
Data Sheet