mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 111

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.11.4
2.11.4.1
The MT90502 uses up to 4 external SSRAM chips and 2 external SDRAM chips on 2 banks for its memory
requirements. SSRAM chips can be 128 KByte, 256 KByte, 512 KByte or 1 MByte in size. The size of SDRAM
chips is either 4Mx16 or 8Mx16. The address and data pins of the memories are shared on either bank (e.g.,
SDRAM A and SSRAM A share their pins). For applications of 512 channels or less, it is possible to use bank A
only. Both banks must be used if sar_capacity is set to 1023.
If only 1 bank is employed, TX SSRAM starts from the beginning of bank A, which is 400000h. RX SSRAM starts
from rx_base_address programmed in register 242h. If using two banks, however, bank A is always TX SSRAM
and bank B is RX SSRAM.
A memory controller is used to multiplex the accesses required of these memories. This dual memory controller
grants the memory bus to the various agents within the chip in order of urgency, using a priority algorithm, and
transforms the memory accesses into the correct pin signals.
2.11.4.2
The memory controller is responsible for generating even parity on the parity pins of the memories and detecting
that the parity is correctly received when reading data from the memory. The MT90502 calculates even parity on all
address bits and data bits used to generate each access. When reading from the memory, it performs the same
calculation in the opposite direction. Parity errors are reported to register 202h. To render parity generation and
detection, configurable masks can be employed to calculate parity on certain bits (registers 230h, 232h and 234h).
Parity is calculated on all locations in memory except for the RX circular buffers, in which the parity bits are used for
underrun information. It is possible to override this and use parity on these circular buffers through control bits in
register 230h.
The controller ensures that the SDRAMs are refreshed often enough to avoid corrupt data. A limit (register 254h)
exists for how many refresh periods behind the SDRAM can be before a status error is generated. SDRAM is
configurable in registers 250h-25Ah.
2.11.5
The SSRAM parity generation and checking can be configured by programming registers 230h mem_parity0, 232h
mem_parity1 and 234h mem_parity2. The SSRAM sizes can be configured by programming registers 240h
mem_conf0 and 242h mem_conf1 (not programmed if using bank B for RX).
The SDRAM can be configured by a series of register writes. Pre-charge all the SDRAM banks, program the mode,
perform a CBR refresh (twice), enable the SDRAM and then set the SDRAM for normal operation.
2.11.6
SSRAM memory chips must be ZBT (zero-bus turnaround) and must be pipelined. SDRAM memory chip must
have A12-A13 as bank select pins, A0-A11 as row address and A0-A7/A8 as column address.
Typical application circuits for Bank A SSRAM and Bank A SDRAM are shown in Figure 69 on page 112 and
Figure 70 on page 113.
Memory Controller
Initializing SSRAM and SDRAM
Memory Configuration
Overview
Functionality
Zarlink Semiconductor Inc.
MT90502
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Data Sheet