mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 126

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 228h
Label: rxa_clk_gen
Reset Value: 0403h
rxa_clk_div[5:0]
rxa_clk_divisor_load_now
rxa_clk_inv
rxa_clk_src[2:0]
rxa_clk_oe
rxa_clk_present
rxa_clk_divisor_reset
reserved
Label
Table 55 - Rx A Clock Division Register
Bit Position Type
15:14
10:8
5:0
12
13
11
6
7
Zarlink Semiconductor Inc.
PUL This bit, when written to '1', will force the new rxa_clk_div
RW Set to '1' when the rxa_clk is present. If the user does not
RW rxa_clk clock source division value. The rxa_clk clock
RW When '1', the rxa_clk's source will be inverted before being
RW “000”=txa_clk_in; “001”=txb_clk_in; “010”=txc_clk_in;
RW rxa_clk output enable. Active high.
RW When '0', will reset the clock division.
RW Reserved. Must always be “00”
MT90502
126
source (selected using rxa_clk_src) can be divided before
being sent out on UTOPIA. Note that odd values will force
the duty cycle to be maintained, rather than returning it to
50-50.
to be applied immediately (possibly causing glitches on
the rxa_clk). This bit should only be set to one when
loading the divisor when the rxa_clk_present bit is
cleared.
Note that it is possible to dynamically change the divisor
value without causing glitches on the output clock if this bit
is not written to 1.
driven out on the rxa_clk pin.
“011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in;
“110”=mem_clk; others=reserved.
want to use the txa UTOPIA interface, this bit should be
left at '0' regardless of the presence of the rxa_clk.
Description
Data Sheet