mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 81

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.7.6
Fast_clk is used internally by the MT90502 as its main operating clock. The internal logic used to generate fast_clk
is show in Figure 44 on page 81. Typically mem_clk would be selected using pll_source.
The pll_div_x and pll_div_y should be programmed according to Figure 44, “Fast Clock Generation,” on page 81.
The fast_clk frequency is given by the formula
H.100/H.110 Clock Selection Guide
upclk/mem_clk (MHz)
Table 27 - Fast Clock PLL Divisor Values
pll_bypass
pll_source
pll_div_x
pll_div_y
fast_clk
Table 28 - Fast Clock Registers
Figure 44 - Fast Clock Generation
Label
>75
>66
>50
>40
>30
>25
Zarlink Semiconductor Inc.
=
input_frequency
MT90502
Register
16Ch
16Ch
16Ch
16Ch
81
pll_div_x
·
1
2
1
1
1
1
×
Bit Position
pll_div_y
---------------------- -
pll_div_x
3:1
6:4
7
8
pll_div_y
.
2
5
3
4
5
6
Data Sheet