mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 203

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

5.4
CNT: Counter. Events in the MT90502 will cause the counter to increment.
CRL: Counter Roll-Over: This bit indicates its respect counter has wrapped.
IE: Interrupt Enable. This is a register bit that enables a status event to generate an interrupt. This bit is always
active-high.
PC: Process Control bit. This is a register bit type that is written to ‘1’ to initiate a hardware process. When the
process completes, the hardware clears the bit.
PUL: Pulse. This bit is used to set an event. Setting this bit, creates a pulse in the MT90502 of 1 clock period. The
hardware then clears this bit.
RO: Read Only. This serves to define registers that cannot be written to by the CPU.
ROL: Read Only Latch. This defines status bits. Status bits cannot be written to ‘1’ by the CPU; however, once the
status bit is set, the CPU can clear it by writing a ‘1’ over it.
RW: Read Write. This type of register bit will be readable and writable by the CPU.
TS: Test Status. This type is for test purposes only and should not be written by the user.
WO: Write Only. This type of register bit is writable by the CPU. The value read back by the CPU may not reflect the
true value of the bit.
5.5
All numbers in this document are decimal unless otherwise specified.
Hexadecimal numbers can be identified by the ‘h’ suffix (e.g. 00A5h).
Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits (e.g. “1001”, ‘0’).
All addresses are specified in hexadecimal and point to bytes.
Addresses are converted from bytes to words to double words using the little endian format, unless otherwise
specified.
Register Types
Units and Conventions
Zarlink Semiconductor Inc.
MT90502
203
Data Sheet