mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 191
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
(204 pages)
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t2_writes1 cpu_rdy_ndtack rising edge to write_access_active rising edge
t2_writes2 cpu_rdy_ndtack rising edge to cpu_d invalid
t1_muxed write_access_active falling edge to cpu_ale fall
t2_muxed cpu_rdy_ndtack rising edge to cpu_ale rising edge
t1_writes write_access_active falling edge to cpu_d valid
Symbol
(when both CS and RD are low)
t15
t16
t17
t4
t5
t6
read_access_active
cpu_rdy_ndtack
write_access_active falling edge to cpu_rdy_ndtack falling edge
Write Access Time
write_access_active rising edge to cpu_rdy_ndtack tri-state
cpu_ale high pulse width
cpu_d valid to cpu_ale falling edge
cpu_ale falling edge to cpu_d invalid
cpu_d[15:0]
cpu_ale
Table 206 - Multiplexed CPU Interface - Intel Mode - Write Access
Figure 76 - Multiplexed CPU Interface - Intel Mode - Read Access
t15
Description
t1
t4
t16
t17
t8
Zarlink Semiconductor Inc.
MT90502
t5
191
t2_muxed
t13
t2_reads
Min. Typical
t6
0
0
0
0
0
5
5
5
2 * upclk - 4 ns
2 * upclk - 4 ns
Max.
740
Data Sheet
12
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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