mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 115

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mt90502ag2

Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
Address: 104h
Label: status0_ie
Reset Value: 0000h
reserved
internal_read_timeout_ie
cpu_read_done_ie
reserved
Address: 108h
Label: mem_clk_freq
Reset Value: 0000h
reserved
mem_clk_freq_integer
reserved
Address: 10Ah
Label: upclk_freq
Reset Value: 0000h
reserved
upclk_freq_integer
reserved
Label
Label
Label
Bit Position
Bit Position
15:11
Bit Position
10:4
3:0
15:11
Table 38 - Mem_clk Frequency Control Register
10:4
3:0
Table 39 - Upclk Frequency Control Register
15:5
2:0
3
4
Table 37 - CPU Interrupt Enable Register
Type
RW
RW
RO
Type
RW Frequency of mem_clk in MHz.
RW Reserved. Must always be “0000”
RO Reserved
Type
RO
RO
IE
IE
Zarlink Semiconductor Inc.
Reserved
Frequency of upclk in MHz.
Reserved. Must always be “0000”
MT90502
Reserved. Always read as “000”
When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
Reserved. Always read as “0000_0000_000”
115
Description
Description
Description
Data Sheet

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