LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 131

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080)
9.5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090)
9.5.6 GPIO interrupt registers
The following registers configure the pins of Port 0 and Port 2 to generate interrupts.
This read-only register indicates the presence of interrupt pending on all of the GPIO ports
that support GPIO interrupts. Only status one bit per port is required.
Table 113. GPIO overall Interrupt Status register (IOIntStatus - address 0x4002 8080) bit
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding port 0 pin.
Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit
Bit
0
1
2
31:2
Bit
0
1
2
3
4
5
6
7
8
9
10
11
14:12 -
15
16
Symbol
P0Int
-
P2Int
-
Symbol
P0.0ER
P0.1ER
P0.2ER
P0.3ER
P0.4ER
P0.5ER
P0.6ER
P0.7ER
P0.8ER
P0.9ER
P0.10ER
P0.11ER
P0.15ER
P0.16ER
description
description
[1]
[1]
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
-
0
1
-
Value Description
0
1
Rev. 2 — 19 August 2010
Port 0 GPIO interrupt pending.
There are no pending interrupts on Port 0.
There is at least one pending interrupt on Port 0.
Reserved. The value read from a reserved bit is not defined.
Port 2 GPIO interrupt pending.
There are no pending interrupts on Port 2.
There is at least one pending interrupt on Port 2.
Reserved. The value read from a reserved bit is not defined.
Enable rising edge interrupt for P0.0.
Rising edge interrupt is disabled on P0.0.
Rising edge interrupt is enabled on P0.0.
Enable rising edge interrupt for P0.1.
Enable rising edge interrupt for P0.2.
Enable rising edge interrupt for P0.3.
Enable rising edge interrupt for P0.4.
Enable rising edge interrupt for P0.5.
Enable rising edge interrupt for P0.6.
Enable rising edge interrupt for P0.7.
Enable rising edge interrupt for P0.8.
Enable rising edge interrupt for P0.9.
Enable rising edge interrupt for P0.10.
Enable rising edge interrupt for P0.11.
Enable rising edge interrupt for P0.15.
Enable rising edge interrupt for P0.16.
Reserved
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
UM10360
© NXP B.V. 2010. All rights reserved.
131 of 840
Reset
value
0
NA
0
NA
Reset
value
0
0
0
0
0
0
0
0
0
NA
0
0
0
0
0