LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 437

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.7.7 Serial clock generator
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 92
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.
This programmable clock pulse generator provides the SCL clock pulses when the I
block is in the master transmitter or master receiver mode. It is switched off when the I
block is in a slave mode. The I
Fig 91. Arbitration procedure
Fig 92. Serial clock synchronization
(1) Another device transmits serial data.
(2) Another device overrules a logic (dotted line) transmitted this I
(3) This I
(1) Another device pulls the SCL line low before this I
(2) Another device continues to pull the SCL line low after this I
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
low. Arbitration is lost, and this I
transmitted. This I
the new master once it has won arbitration.
device effectively determines the (shorter) HIGH period.
released SCL. The I
effectively determines the (longer) LOW period.
SDA line
SCL line
shows the synchronization procedure.
SDA line
SCL line
2
C is in Slave Receiver mode but still generates clock pulses until the current byte has been
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
2
C will not generate clock pulses for the next byte. Data on SDA originates from
2
C clock generator is forced to wait until SCL goes HIGH. The other device
(1)
1
period
high
2
C block will stretch the SCL space duration after a byte has
2
C output clock frequency and duty cycle is programmable
(1)
(1)
2
2
C enters Slave Receiver mode.
period
low
(2)
3
(2)
(3)
4
2
C has timed a complete high time. The other
(1)
2
Chapter 19: LPC17xx I2C0/1/2
(3)
C has timed a complete low time and
2
C master by pulling the SDA line
8
UM10360
© NXP B.V. 2010. All rights reserved.
ACK
9
437 of 840
2
C
2
C