LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 693

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.6.1.1 Syntax
34.2.6.1.2 Operation
34.2.6.1.3 Restrictions
34.2.6.1.4 Condition flags
34.2.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and
producing a 32-bit result.
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond is an optional condition code, see
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
The MUL instruction multiplies the values from Rn and Rm, and places the least significant
32 bits of the result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and
places the least significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the
value from Ra, and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or
unsigned.
In these instructions, do not use SP and do not use PC.
If you use the S suffix with the MUL instruction:
If S is specified, the MUL instruction:
•
•
•
•
•
Rd, Rn, and Rm must all be in the range R0 to R7
Rd must be the same as Rm
you must not use the cond suffix.
updates the N and Z flags according to the result
does not affect the C and V flags.
All information provided in this document is subject to legal disclaimers.
Section 34.2.3.7 “Conditional
Rev. 2 — 19 August 2010
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
execution”.
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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