LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 358
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
UM10360
User manual
Bit
5
6
7
8
9
10
15:11 -
Symbol
EPI
ALI
BEI
IDI
TI2
TI3
bit description
Value
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
-
Function
Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the
CAN controller switches between Error Passive and Error Active mode in either
direction.
This is the case when the CAN Controller has reached the Error Passive Status
(at least one error counter exceeds the CAN protocol defined level of 127) or if
the CAN Controller is in Error Passive Status and enters the Error Active Status
again.
Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the
CAN controller loses arbitration while attempting to transmit. In this case the
CAN node becomes a receiver.
Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN
controller detects an error on the bus.
ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN
Identifier has been received (a message was successfully transmitted or
aborted). This bit is set whenever a message was successfully transmitted or
aborted and the IDIE bit is set in the IER register.
Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to
1 (whenever a message out of TXB2 was successfully transmitted or aborted),
indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.
Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to
1 (whenever a message out of TXB3 was successfully transmitted or aborted),
indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.
Reserved, user software should not write ones to reserved bits.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
0
Reset
Value
0
0
0
0
0
0
358 of 840
RM
Set
0
0
X
0
0
0
0
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