LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 346

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 54. Transmit buffer layout for standard and extended frame format configurations
31
31
TX
TX
0 0 0
16.5.4 Receive Buffer (RXB)
TX Data 4
TX Data 8
TX Data 4
TX Data 8
Frame info
Frame info
ID.28
The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is
located between the CAN Controller Core Block and APB Interface Block and stores all
received messages from the CAN Bus line. With the help of this Double Receive Buffer
concept the CPU is able to process one message while another message is being
received.
The global layout of the Receive Buffer is very similar to the Transmit Buffer described
earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length
Code have the same meaning as described for the Transmit Buffer. In addition, the
Receive Buffer includes an ID Index field (see
The received Data Length Code represents the real transmitted Data Length Code, which
may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum
number of received data bytes is 8. This should be taken into account by reading a
message from the Receive Buffer. If there is not enough space for a new message within
the Receive Buffer, the CAN Controller generates a Data Overrun condition when this
message becomes valid and the acceptance test was positive. A message that is partly
written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This
situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if
enabled.
24 23
24 23
0 . . . 0
unused
unused
TX Data 3
TX Data 7
TX Data 3
TX Data 7
TX DLC
TX DLC
All information provided in this document is subject to legal disclaimers.
Extended Frame Format (29-bit Identifier)
Standard Frame Format (11-bit Identifier)
16 15
16 15
...
Rev. 2 — 19 August 2010
TX Data 2
TX Data 6
TX Data 2
TX Data 6
unused
unused
8 7
8 7
ID.28 ... ID.18
TX Priority
TX Priority
TX Data 1
TX Data 5
TX Data 1
TX Data 5
ID.00
Section 16.7.9.1 “ID index
0
0
TDA
TDB
TDA
TDB
TFS
TFS
TID
TID
Chapter 16: LPC17xx CAN1/2
Descriptor
Data Field
Descriptor
Data Field
Field
Field
UM10360
© NXP B.V. 2010. All rights reserved.
field”).
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