LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 446

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.8.6 I
19.8.7 I
0x4001 C02C; I
I2C2DATA_BUFFER- 0x400A 002C)
In monitor mode, the I
bit is not set. This means that the processor will have a limited amount of time to read the
contents of the data received on the bus. If the processor reads the I2DAT shift register, as
it ordinarily would, it could have only one bit-time to respond to the interrupt before the
received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only I2DATA_BUFFER
register will be added. The contents of the 8 MSBs of the I2DAT shift register will be
transferred to the I2DATA_BUFFER automatically after every 9 bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have 9
bit transmission times to respond to the interrupt and read the data before it is overwritten.
The processor will still have the ability to read I2DAT directly, as usual, and the behavior of
I2DAT will not be altered in any way.
Although the I2DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
Table 389. I
0x4001 C0[0C, 20, 24, 28]; I
0x4005 C0[0C, 20, 24, 28]; I
0x400A 00[0C, 20, 24, 28])
These registers are readable and writable and are only used when an I
to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If these registers contain 0x00, the I
four registers will be cleared to this disabled state on reset.
Table 390. I
Bit
7:0
31:8
Bit
0
7:1
31:8
2
2
C Data buffer register (I2DATA_BUFFER: I
C Slave Address registers (I2ADR0 to 3: I
Symbol Description
Data
-
Symbol
GC
Address
-
0x4001 C02C; I
0x400A 002C) bit description
20, 24, 28]; I
I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]) bit description
2
2
C Data buffer register (I2DATA_BUFFER: I
C Slave Address registers (I2ADR0 to 3: I
All information provided in this document is subject to legal disclaimers.
This register holds contents of the 8 MSBs of the I2DAT shift register.
Reserved. The value read from a reserved bit is not defined.
Description
General Call enable bit.
The I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
C1, I2C1DATA_BUFFER- 0x4005 C02C; I
2
2
2
Rev. 2 — 19 August 2010
C module may lose the ability to stretch the clock if the ENA_SCL
C device address for slave mode.
C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I
2
C1, I2C1DATA_BUFFER- 0x4005 C02C; I
2
2
C1, I2C1ADR[0, 1, 2, 3] - address
C2, I2C2ADR[0, 1, 2, 3] - address
2
C will not acknowledge any address on the bus. All
2
2
C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C,
C0, I2CDATA_BUFFER -
2
2
C0, I2C0ADR[0, 1, 2, 3]-
C0, I2CDATA_BUFFER -
Chapter 19: LPC17xx I2C0/1/2
2
C2, I2C2DATA_BUFFER-
UM10360
2
© NXP B.V. 2010. All rights reserved.
2
C interface is set
C2,
446 of 840
2
C2,
Reset
value
0
NA
Reset
value
0
0x00
NA