LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 434

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
19.7 I
UM10360
User manual
2
C implementation and operation
19.6.4 Slave Transmitter mode
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I
operate as a master and as a slave. In the slave mode, the I
its own slave addresses and the General Call address. If one of these addresses is
detected, an interrupt is requested. When the microcontrollers wishes to become the bus
master, the hardware waits until the bus is free before the master mode is entered so that
a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the
I
addresses in the same serial transfer.
Figure 90
describes the individual blocks.
2
Fig 88. Format of Slave Receiver mode
Fig 89. Format of Slave Transmitter mode
C interface switches to the slave mode immediately and can detect any of its own slave
S
from Master to Slave
from Slave to Master
S
from Master to Slave
from Slave to Master
SLAVE ADDRESS
SLAVE ADDRESS
shows how the on-chip I
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
RW=1
RW=0
2
C-bus interface is implemented, and the following text
A
A
DATA
DATA
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Sr = Repeated START condition
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
n bytes data transmitted
n bytes data received
A
A
Chapter 19: LPC17xx I2C0/1/2
2
C hardware looks for any of
DATA
DATA
UM10360
© NXP B.V. 2010. All rights reserved.
A/A
A
2
434 of 840
C may
P/Sr
P