LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 476

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
20.5 Register description
Table 404. I
Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description
UM10360
User manual
Name
I2SDAO
I2SDAI
I2STXFIFO
I2SRXFIFO
I2SSTATE
I2SDMA1
I2SDMA2
I2SIRQ
I2STXRATE
I2SRXRATE
I2STXBITRATE Transmit bit rate divider. This register determines the I
I2SRXBITRATE Receive bit rate divider. This register determines the I
I2STXMODE
I2SRXMODE
Bit
1:0
Symbol
wordwidth
2
S register map
20.5.1 Digital Audio Output register (I2SDAO - 0x400A 8000)
Description
Digital Audio Output Register. Contains control bits for the I
channel.
Digital Audio Input Register. Contains control bits for the I
channel.
Transmit FIFO. Access register for the 8
Receive FIFO. Access register for the 8
Status Feedback Register. Contains status information about the I
interface.
DMA Configuration Register 1. Contains control information for DMA
request 1.
DMA Configuration Register 2. Contains control information for DMA
request 2.
Interrupt Request Control Register. Contains bits that control how the
I
Transmit MCLK divider. This register determines the I
by specifying the value to divide PCLK by in order to produce MCLK.
Receive MCLK divider. This register determines the I
by specifying the value to divide PCLK by in order to produce MCLK.
rate by specifying the value to divide TX_MCLK by in order to produce
the transmit bit clock.
by specifying the value to divide RX_MCLK by in order to produce the
receive bit clock.
Transmit mode control.
Receive mode control.
2
S interrupt request is generated.
Value Description
Table 404
functions. Following the table are details for each register.
[1]
The I2SDAO register controls the operation of the I
bits in DAO are shown in
00
01
10
11
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Selects the number of bytes in data as follows:
8-bit data
16-bit data
Reserved, do not use this setting
32-bit data
shows the registers associated with the I
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
×
×
32-bit receiver FIFO.
405.
32-bit transmitter FIFO.
2
2
2
S RX MCLK rate
S receive bit rate
2
S TX MCLK rate
S transmit bit
2
S receive
2
S transmit
2
2
S interface and a summary of their
S transmit channel. The function of
2
S
Access Reset
R/W
R/W
WO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Chapter 20: LPC17xx I2S
0x87E1 0x400A 8000
0x07E1 0x400A 8004
0
0
0
0
0
Value
0x7
0
0
0
0
0
0
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
Address
0x400A 8008
0x400A 800C
0x400A 8010
0x400A 8014
0x400A 8018
0x400A 801C
0x400A 8020
0x400A 8024
0x400A 8028
0x400A 802C
0x400A 8030
0x400A 8034
476 of 840
Reset
Value
01