LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 163

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
10.12.14 Transmit Status Vector 1 Register (TSV1 - 0x5000 015C)
distributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.
Table 160
Table 160. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description
[1]
The Transmit Status Vector 1 register (TSV1) is a read-only register with an address of
0x5000 015C. The transmit status vector registers store the most recent transmit status
returned by the MAC. Since the status vector consists of more than 4 bytes, status is
distributed over two registers TSV0 and TSV1. These registers are provided for debug
Bit
0
1
2
3
4
5
6
7
8
9
10
11
27:12 Total bytes
28
29
30
31
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
Symbol
CRC error
Length check error
Length out of range
Done
Multicast
Broadcast
Packet Defer
Excessive Defer
Excessive Collision
Late Collision
Giant
Underrun
Control frame
Pause
Backpressure
VLAN
lists the bit definitions of the TSV0 register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
[1]
Indicates the frame length field does not match the actual
Packet was aborted due to exceeding of maximum allowed
Collision occurred beyond collision window, 512 bit times.
Host side caused buffer underrun.
The frame was a control frame.
The frame was a control frame with a valid PAUSE
Frame’s length/type field contained 0x8100 which is the
Function
The attached CRC in the packet did not match the
internally generated CRC.
number of data items and is not a type field.
Indicates that frame type/length field was larger than
1500 bytes.
Transmission of packet was completed.
Packet’s destination was a multicast address.
Packet’s destination was a broadcast address.
Packet was deferred for at least one attempt, but less than
an excessive defer.
Packet was deferred in excess of 6071 nibble times in
100 Mbps or 24287 bit times in 10 Mbps mode.
number of collisions.
Byte count in frame was greater than can be represented
in the transmit byte count field in TSV1.
The total number of bytes transferred including collided
attempts.
opcode.
Carrier-sense method backpressure was previously
applied.
VLAN protocol identifier.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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0
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0x0
0
0
0
0