LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 536

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 477. MCPWM Capture read addresses (MCCAP0/1/2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) bit description
UM10360
User manual
Bit
31:0
25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048,
25.7.10.2 MCPWM Capture clear address (MCCAP_CLR - 0x400B 8074)
Symbol
CAP0/1/2
25.7.10 MCPWM Capture Registers
0x400B 804C)
The MCCAPCON register
MCI0-2 inputs as a capture event for each channel. When a channel’s capture event
occurs, the current TC value for that channel is stored in its read-only Capture register.
These addresses are read-only, but the underlying registers can be cleared by writing to
the CAP_CLR address
Writing ones to this write-only address clears the selected CAP register(s).
Table 478. MCPWM Capture clear address (CAP_CLR - 0x400B 8074) bit description
Bit
0
1
2
31:3
Description
TC value at a capture event for channels 0, 1, 2.
Symbol
CAP_CLR0
CAP_CLR1
CAP_CLR2
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Description
Writing a 1 to this bit clears the MCCAP0 register.
Writing a 1 to this bit clears the MCCAP1 register.
Writing a 1 to this bit clears the MCCAP2 register.
Reserved
(Table
458) allows software to select any edge(s) on any of the
Chapter 25: LPC17xx Motor control PWM
UM10360
© NXP B.V. 2010. All rights reserved.
0x0000 0000
Reset value
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