LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 757

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.3.5.1.3 Sleep-on-exit
34.3.5.2.1 Wakeup from WFI or sleep-on-exit
34.3.5.2.2 Wakeup from WFE
34.3.5.2 Wakeup from sleep mode
34.3.5.3 The Wake-up Interrupt Controller
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the
execution of an exception handler it returns to Thread mode and immediately enters sleep
mode. Use this mechanism in applications that only require the processor to run when an
exception occurs.
The conditions for the processor to wakeup depend on the mechanism that cause it to
enter sleep mode.
Normally, the processor wakes up only when it detects an exception with sufficient priority
to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK
bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a
higher priority than current exception priority, the processor wakes up but does not
execute the interrupt handler until the processor sets PRIMASK to zero. For more
information about PRIMASK and FAULTMASK see
The processor wakes up if:
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt
triggers an event and wakes up the processor, even if the interrupt is disabled or has
insufficient priority to cause exception entry. For more information about the SCR see
Section 34.4.3.7 “System Control
The Wake-up Interrupt Controller (WIC) is a peripheral that can detect an interrupt and
wake the processor from Deep sleep mode, Power-down mode, or Deep power-down
mode. The WIC is enabled only when the DEEPSLEEP bit in the SCR is set to 1, see
Section 34.4.3.7 “System Control
Details of wake-up possibilities on the LPC17xx can be found in
control”.
The WIC is not programmable, and does not have any registers or user interface. It
operates entirely from hardware signals.
When the WIC is enabled and the processor enters deep sleep mode or Power-down
mode, the power management unit in the system can power down most of the Cortex-M3
processor. This has the side effect of stopping the SysTick timer. When the WIC receives
an interrupt, it takes a number of clock cycles to wakeup the processor and restore its
state, before it can process the interrupt. This means interrupt latency is increased in deep
sleep mode. Wake-up from Power-down mode requires startup of many other portions of
the device, and takes longer. Wake-up from Deep Power-down mode adds time to
re-establish the on-chip regulator voltage as well.
•
it detects an exception with sufficient priority to cause exception entry
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Register”.
Register”.
Chapter 34: Appendix: Cortex-M3 user guide
Section
34.3.1.3.6.
Section 4.8 “Power
UM10360
© NXP B.V. 2010. All rights reserved.
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