LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 165

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
10.12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170)
10.12.17 Flow Control Status Register (FlowControlStatus - 0x5000 0174)
Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description
[1]
The Flow Control Counter register (FlowControlCounter) has an address of 0x5000 0170.
Table 163
Table 163. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit
The Flow Control Status register (FlowControlStatus) is a read-only register with an
address of 0x5000 0174.
Table 164. Flow Control Status register (FlowControlStatus - address 0x5000 0174) bit
Bit
26
27
28
29
30
31
Bit
15:0
31:16 PauseTimer
Bit
15:0
31:16 -
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
Symbol
Dribble Nibble
Control frame
PAUSE
Unsupported Opcode The current frame was recognized as a Control Frame but
VLAN
-
Symbol
MirrorCounter
Symbol
MirrorCounterCurrent In full duplex mode this register represents the current
lists the bit definitions of the register.
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 164
The frame was a control frame.
Frame’s length/type field contained 0x8100 which is the
In full duplex mode the MirrorCounter specifies the number
In full-duplex mode the PauseTimer specifies the value
Function
Indicates that after the end of packet another 1-7 bits were
received. A single nibble, called dribble nibble, is formed
but not sent out.
The frame was a control frame with a valid PAUSE
opcode.
contains an unknown opcode.
VLAN protocol identifier.
Unused
Function
of cycles before re-issuing the Pause control frame.
that is inserted into the pause timer field of a pause flow
control frame. In half duplex mode the PauseTimer
specifies the number of backpressure cycles.
Function
value of the datapath’s mirror counter which counts up to
the value specified by the MirrorCounter field in the
FlowControlCounter register. In half duplex mode the
register counts until it reaches the value of the PauseTimer
bits in the FlowControlCounter register.
Unused
lists the bit definitions of the register.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
165 of 840
Reset
value
0
0
0
0
0
0x0
Reset
value
0x0
0x0
Reset
value
0x0
0x0