LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 529

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 459. MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description
Table 460. MCPWM Capture control clear register (MCCAPCON_CLR - address 0x400B 8014) bit description
Table 462. Interrupt sources bit allocation table
UM10360
User manual
Bit
31:0
Bit
31:0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Description
Description
Writing ones to this address clears the corresponding bits in the MCCAPCON register. See
Writing ones to this address sets the corresponding bits in the MCCAPCON register. See
25.7.2.2 MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010)
25.7.2.3 MCPWM Capture control clear address (MCCAPCON_CLR - 0x400B 8014)
25.7.3 MCPWM Interrupt registers
7.3.1 MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050)
ABORT
31
23
15
7
-
-
-
Writing ones to this write-only address sets the corresponding bits in MCCAPCON.
Writing ones to this write-only address clears the corresponding bits in MCCAPCON.
The Motor Control PWM module includes the following interrupt sources:
Table 461. Motor Control PWM interrupts
All MCPWM interrupt registers contain one bit for each source as shown in
The MCINTEN register controls which of the MCPWM interrupts are enabled. This
address is read-only, but the underlying register can be modified by writing to addresses
MCINTEN_SET and MCINTEN_CLR.
Table 463. MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050) bit description
Symbol
ILIM0/1/2
IMAT0/1/2
ICAP0/1/2
ABORT
Bit
31:0
ICAP1
30
22
14
6
-
-
-
Value Description
1
0
All information provided in this document is subject to legal disclaimers.
IMAT1
See
Interrupt enabled.
Interrupt disabled.
Description
Limit interrupts for channels 0, 1, 2.
Match interrupts for channels 0, 1, 2.
Capture interrupts for channels 0, 1, 2.
Fast abort interrupt
29
21
13
5
-
-
-
Table 462
Rev. 2 — 19 August 2010
ILIM1
for the bit allocation.
28
20
12
4
-
-
-
27
19
11
3
Chapter 25: LPC17xx Motor control PWM
-
-
-
-
ICAP2
ICAP0
26
18
10
2
-
-
Table
IMAT2
IMAT0
Table
25
17
UM10360
9
1
-
-
© NXP B.V. 2010. All rights reserved.
458.
458.
Table
Reset
value
0
ILIM2
ILIM0
529 of 840
462.
24
16
8
0
-
-