LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 220
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
11.10 Register description
Table 188. USB device register map
UM10360
User manual
Name
Clock control registers
USBClkCtrl
USBClkSt
Device interrupt registers
USBIntSt
USBDevIntSt
USBDevIntEn
USBDevIntClr
USBDevIntSet
USBDevIntPri
Endpoint interrupt registers
USBEpIntSt
USBEpIntEn
USBEpIntClr
USBEpIntSet
USBEpIntPri
Endpoint realization registers
USBReEp
USBEpIn
USBMaxPSize
USB transfer registers
USBRxData
USBRxPLen
USBTxData
USBTxPLen
USBCtrl
SIE Command registers
USBCmdCode
USBCmdData
11.9.4 Remote wake-up
The USB device controller supports software initiated remote wake-up. Remote wake-up
involves resume signaling on the USB bus initiated from the device. This is done by
clearing the SUS bit in the SIE Set Device Status register. Before writing into the register,
all the clocks to the device controller have to be enabled using the USBClkCtrl register.
Table 188
Serial Interface Engine (SIE) has other registers that are indirectly accessible via the SIE
command registers. See
more info.
Description
USB Clock Control
USB Clock Status
USB Interrupt Status
USB Device Interrupt Status
USB Device Interrupt Enable
USB Device Interrupt Clear
USB Device Interrupt Set
USB Device Interrupt Priority
USB Endpoint Interrupt Status
USB Endpoint Interrupt Enable
USB Endpoint Interrupt Clear
USB Endpoint Interrupt Set
USB Endpoint Priority
USB Realize Endpoint
USB Endpoint Index
USB MaxPacketSize
USB Receive Data
USB Receive Packet Length
USB Transmit Data
USB Transmit Packet Length
USB Control
USB Command Code
USB Command Data
shows the USB Device Controller registers directly accessible by the CPU. The
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 11.12 “Serial interface engine command description”
Chapter 11: LPC17xx USB device controller
Access
R/W
RO
R/W
RO
R/W
WO
WO
WO
RO
R/W
WO
WO
WO
R/W
WO
R/W
RO
RO
WO
WO
R/W
WO
RO
[2]
[2]
[2]
[2]
[2]
Reset value
0
0
0x8000 0000
0x10
0
0
0
0
0
0
0
0
0
0x3
0
0x8
0
0
0
0
0
0
0
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
Address
0x5000 CFF4
0x5000 CFF8
0x400F C1C0
0x5000 C200
0x5000 C204
0x5000 C208
0x5000 C20C
0x5000 C22C
0x5000 C230
0x5000 C234
0x5000 C238
0x5000 C23C
0x5000 C240
0x5000 C244
0x5000 C248
0x5000 C24C
0x5000 C218
0x5000 C220
0x5000 C21C
0x5000 C224
0x5000 C228
0x5000 C210
0x5000 C214
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