LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 351

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 315. CAN1 and CAN2 controller register summary
Table 316. CAN Wake and Sleep registers
UM10360
User manual
Generic
Name
MOD
CMR
GSR
ICR
IER
BTR
EWL
SR
RFS
RID
RDA
RDB
TFI1
TID1
TDA1
TDB1
Name
CANSLEEPCLR
CANWAKEFLAGS Allows reading the wake-up state of the CAN channels.
Operating Mode
Read
Mode
0x00
Global Status and Error Counters
Interrupt and Capture
Interrupt Enable
Bus Timing
Error Warning Limit
Status
Rx Info and Index
Rx Identifier
Rx Data
Rx Info and Index
Tx Info1
Tx Identifier
Tx Data
Tx Data
16.7.1
Description
Allows clearing the current CAN channel sleep state as well as
reading that state.
The internal registers of each CAN Controller appear to the CPU as on-chip memory
mapped peripheral registers. Because the CAN Controller can operate in different modes
(Operating/Reset, see also
0x4004 4000, CAN2MOD - 0x4004
internal address definitions. Note that write access to some registers is only allowed in
Reset Mode.
In the following register tables, the column “Reset Value” shows how a hardware reset
affects each bit or field, while the column “RM Set” indicates how each bit or field is
affected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note that
while hardware reset sets RM, in this case the setting noted in the “Reset Value” column
prevails over that shown in the “RM Set” column, in the few bits where they differ. In both
columns, X indicates the bit or field is unchanged.
CAN Mode r
0x4004 8000)
The contents of the Mode Register are used to change the behavior of the CAN
Controller. Bits may be set or reset by the CPU that uses the Mode Register as a
read/write memory.
All information provided in this document is subject to legal disclaimers.
egister (CAN1MOD - 0x4004 4000, CAN2MOD -
Write
Mode
Command
-
-
Interrupt Enable
-
-
-
-
-
-
-
Tx Info
Tx Identifier
Tx Data
Tx Data
Rev. 2 — 19 August 2010
Section 16.7.1 “CAN Mode register (CAN1MOD -
8000)”), one has to distinguish between different
Reset Mode
Read
Mode
0x00
Global Status and Error Counters
Interrupt and Capture
Interrupt Enable
Bus Timing
Error Warning Limit
Status
Rx Info and Index
Rx Identifier
Rx Data
Rx Info and Index
Tx Info
Tx Identifier
Tx Data
Tx Data
R/W
Access
R/W
Chapter 16: LPC17xx CAN1/2
Reset Value Address
0
0
UM10360
Write
Mode
Command
Error Counters only
-
Interrupt Enable
Bus Timing
Error Warning Limit
-
Rx Info and Index
Rx Identifier
Rx Data
Rx Info and Index
Tx Info
Tx Identifier
Tx Data
Tx Data
© NXP B.V. 2010. All rights reserved.
0x400F C110
0x400F C114
351 of 840