LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 223

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description
Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation
Reset value: 0x0000 0000
Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description
UM10360
User manual
Bit
8
30:9
31
Bit
0
1
2
3
4
5
6
7
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
USB_NEED_CLK
-
EN_USB_INTS
Symbol
FRAME
EP_FAST
EP_SLOW
DEV_STAT
CCEMPTY
CDFULL
RxENDPKT
TxENDPKT
11.10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200)
TxENDPKT
31
23
15
7
-
-
-
Description
The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.
Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set,
the corresponding endpoint interrupt will be routed to this bit.
Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is
not set, the corresponding endpoint interrupt will be routed to this bit.
Set when USB Bus reset, USB suspend change or Connect change event occurs.
Refer to
page
The command code register (USBCmdCode) is empty (New command can be written). 1
Command data register (USBCmdData) is full (Data can be read now).
The current packet in the endpoint buffer is transferred to the CPU.
The number of data bytes transferred to the endpoint buffer equals the number of bytes
programmed in the TxPacket length register (USBTxPLen).
The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and
1 indicates the presence of the interrupt. USBDevIntSt is a read-only register.
247.
ENDPKT
Section 11.12.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on
Description
USB need clock indicator. This bit is set to 1 when USB activity or a change
of state on the USB data pins is detected, and it indicates that a PLL supplied
clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets
to zero 5 ms after the last packet has been received/sent, or 2 ms after the
Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from
0 to 1 can wake up the microcontroller if activity on the USB bus is selected
to wake up the part from the Power-down mode (see
from Reduced Power Modes”
Power-down mode”
register (PCONP - 0x400F C0C4)”
invoking the Power-down mode. This bit is read-only.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Enable all USB interrupts. When this bit is cleared, the Vectored Interrupt
Controller does not see the ORed output of the USB interrupt lines.
Rx
30
22
14
6
-
-
-
All information provided in this document is subject to legal disclaimers.
CDFULL
29
21
13
5
-
-
-
Rev. 2 — 19 August 2010
and
CCEMPTY
Section 4.8.9 “Power Control for Peripherals
28
20
12
4
-
-
-
for details). Also see
for considerations about the PLL and
DEV_STAT
Chapter 11: LPC17xx USB device controller
27
19
11
3
-
-
-
Section 4.5.9 “PLL0 and
EP_SLOW
Section 4.8.8 “Wake-up
26
18
10
2
-
-
-
EP_FAST
ERR_INT
25
17
UM10360
9
1
-
-
© NXP B.V. 2010. All rights reserved.
Reset value
1
NA
1
Reset value
0
0
0
0
0
0
0
EP_RLZED
FRAME
223 of 840
24
16
8
0
-
-