LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 830

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
20.5
20.5.1
20.5.2
20.5.3
20.5.4
20.5.5
20.5.6
20.5.7
20.5.8
Chapter 21: LPC17xx Timer 0/1/2/3
21.1
21.2
21.3
21.4
21.5
21.5.1
21.6
21.6.1
21.6.2
21.6.3
21.6.4
Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT)
22.1
22.2
22.3
22.3.1
Chapter 23: LPC17xx System Tick Timer
23.1
UM10360
User manual
Register description . . . . . . . . . . . . . . . . . . . 476
Basic configuration . . . . . . . . . . . . . . . . . . . . 490
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 491
Register description . . . . . . . . . . . . . . . . . . . 492
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Register description . . . . . . . . . . . . . . . . . . . 501
Basic configuration . . . . . . . . . . . . . . . . . . . . 504
Digital Audio Output register (I2SDAO -
0x400A 8000) . . . . . . . . . . . . . . . . . . . . . . . . 476
Digital Audio Input register (I2SDAI -
0x400A 8004) . . . . . . . . . . . . . . . . . . . . . . . . 477
Transmit FIFO register (I2STXFIFO -
0x400A 8008) . . . . . . . . . . . . . . . . . . . . . . . . 477
Receive FIFO register (I2SRXFIFO -
0x400A 800C). . . . . . . . . . . . . . . . . . . . . . . . 477
Status Feedback register (I2SSTATE -
0x400A 8010) . . . . . . . . . . . . . . . . . . . . . . . . 478
DMA Configuration Register 1 (I2SDMA1 -
0x400A 8014) . . . . . . . . . . . . . . . . . . . . . . . . 478
DMA Configuration Register 2 (I2SDMA2 -
0x400A 8018) . . . . . . . . . . . . . . . . . . . . . . . . 479
Interrupt Request Control register (I2SIRQ -
0x400A 801C). . . . . . . . . . . . . . . . . . . . . . . . 479
Multiple CAP and MAT pins . . . . . . . . . . . . . 491
Interrupt Register (T[0/1/2/3]IR - 0x4000 4000,
0x4000 8000, 0x4009 0000, 0x4009 4000) . 493
Timer Control Register (T[0/1/2/3]CR -
0x4000 4004, 0x4000 8004, 0x4009 0004,
0x4009 4004) . . . . . . . . . . . . . . . . . . . . . . . . 493
Count Control Register (T[0/1/2/3]CTCR -
0x4000 4070, 0x4000 8070, 0x4009 0070,
0x4009 4070) . . . . . . . . . . . . . . . . . . . . . . . . 494
Timer Counter . . . . . . . .registers (T0TC - T3TC,
0x4000 4008, 0x4000 8008, 0x4009 0008,
0x4009 4008) . . . . . . . . . . . . . . . . . . . . . . . . 495
RI Compare Value register (RICOMPVAL -
0x400B 0000) . . . . . . . . . . . . . . . . . . . . . . . . 501
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
20.5.9
20.5.9.1
20.5.10
20.5.11
20.5.12
20.5.13
20.5.14
20.6
20.7
20.8
21.6.5
21.6.6
21.6.7
21.6.8
21.6.9
21.6.10
21.6.11
21.6.12
21.7
21.8
22.3.2
22.3.3
22.3.4
22.4
23.2
I
I
FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 488
Example timer operation . . . . . . . . . . . . . . . 499
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 500
RI timer operation . . . . . . . . . . . . . . . . . . . . . 502
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
2
2
S transmit and receive interfaces . . . . . . . 483
S operating modes . . . . . . . . . . . . . . . . . . . 484
Transmit Clock Rate register (I2STXRATE -
0x400A 8020). . . . . . . . . . . . . . . . . . . . . . . . 479
Notes on fractional rate generators . . . . . . . 480
Receive Clock Rate register (I2SRXRATE -
0x400A 8024). . . . . . . . . . . . . . . . . . . . . . . . 480
Transmit Clock Bit Rate register (I2STXBITRATE
- 0x400A 8028) . . . . . . . . . . . . . . . . . . . . . . 481
Receive Clock Bit Rate register (I2SRXBITRATE -
0x400A 802C) . . . . . . . . . . . . . . . . . . . . . . . 481
Transmit Mode Control register (I2STXMODE -
0x400A 8030). . . . . . . . . . . . . . . . . . . . . . . . 481
Receive Mode Control register (I2SRXMODE -
0x400A 8034). . . . . . . . . . . . . . . . . . . . . . . . 482
Prescale register (T0PR - T3PR, 0x4000 400C,
0x4000 800C, 0x4009 000C, 0x4009 400C) 495
Prescale Counter register (T0PC - T3PC,
0x4000 4010, 0x4000 8010, 0x4009 0010,
0x4009 4010) . . . . . . . . . . . . . . . . . . . . . . . . 495
Match Registers (MR0 - MR3) . . . . . . . . . . . 496
Match Control Register (T[0/1/2/3]MCR -
0x4000 4014, 0x4000 8014, 0x4009 0014,
0x4009 4014) . . . . . . . . . . . . . . . . . . . . . . . . 496
Capture Registers (CR0 - CR1) . . . . . . . . . . 497
Capture Control Register (T[0/1/2/3]CCR -
0x4000 4028, 0x4000 8028, 0x4009 0028,
0x4009 4028) . . . . . . . . . . . . . . . . . . . . . . . . 497
External Match Register (T[0/1/2/3]EMR -
0x4000 403C, 0x4000 803C, 0x4009 003C,
0x4009 403C) . . . . . . . . . . . . . . . . . . . . . . . 497
DMA operation . . . . . . . . . . . . . . . . . . . . . . . 498
RI Mask register (RIMASK - 0x400B 0004) . 501
RI Control register (RICTRL - 0x400B 0008) 502
RI Counter register (RICOUNTER - 0x400B
000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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