LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 484

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
20.7 I
Table 419: I
UM10360
User manual
I2SDAO
[5]
0
0
0
0
1
1
1
2
S operating modes
I2STXMODE
2
S transmit modes
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
0 0 0 0
0 0 1 0
0 1 0 0
[3:0]
The clocking and WS usage of the I
slave modes, which are independently configurable for the transmitter and the receiver,
several different clock sources are possible, including variations that share the clock
and/or WS between the transmitter and receiver. This last option allows using I
fewer pins, typically four.
Many configurations are possible that are not considered useful, the following tables and
figures give details of the configurations that are most likely to be useful.
Description
Typical transmitter master mode. See
The
The transmit clock source is the fractional rate divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.
Transmitter master mode sharing the receiver reference clock. See
The
The transmit clock source is RX_REF.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.
4-wire transmitter master mode sharing the receiver bit clock and WS. See
The
The transmit clock source is the RX bit clock.
The WS used is the internally generated RX_WS.
The TX_MCLK pin is not enabled for output.
Transmitter master mode with TX_MCLK output. See
The
The transmit clock source is the fractional rate divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is enabled for output.
Typical transmitter slave mode. See
The
The transmit clock source is the TX_CLK pin.
The WS used is the TX_WS pin.
Transmitter slave mode sharing the receiver reference clock. See
The
The transmit clock source is RX_REF.
The WS used is the TX_WS pin.
4-wire transmitter slave mode sharing the receiver bit clock and WS. See
The
The transmit clock source is the RX bit clock.
The WS used is RX_WS ref.
I
I
I
I
I
I
I
2
2
2
2
2
2
2
S
S
S
S
S
S
S
transmit function operates as a master.
transmit function operates as a master.
transmit function operates as a master.
transmit function operates as a master.
transmit function operates as a slave.
transmit function operates as a slave.
transmit function operates as a slave.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Figure
Figure
2
S interface is configurable. In addition to master and
104.
101.
Figure
101.
Figure
Figure
Chapter 20: LPC17xx I2S
105.
Figure
102.
Figure
UM10360
© NXP B.V. 2010. All rights reserved.
106.
103.
2
S with
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