LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 672

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.4.6.3 Restrictions
34.2.4.6.4 Condition flags
34.2.4.6.5 Examples
34.2.4.6.6 Incorrect examples
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at
4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in
reglist. The accesses happen in order of decreasing register numbers, with the highest
numbered register using the highest memory address and the lowest number register
using the lowest memory address. If the writeback suffix is specified, the value of
Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See
details.
In these instructions:
When PC is in reglist in an LDM instruction:
These instructions do not change the flags.
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•
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Rn must not be PC
reglist must not contain SP
in any STM instruction, reglist must not contain PC
in any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if you specify the writeback suffix.
bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch
occurs to this halfword-aligned address
if the instruction is conditional, it must be the last instruction in the IT block.
LDM
STMDB
STM
LDM
All information provided in this document is subject to legal disclaimers.
R8,{R0,R2,R9}
R1!,{R3-R6,R11,R12}
R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
R2, {}
Rev. 2 — 19 August 2010
; There must be at least one register in the list
; LDMIA is a synonym for LDM
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.2.4.7
UM10360
© NXP B.V. 2010. All rights reserved.
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