LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 308

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
Table 281: UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -
Table 282: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR -
UM10360
User manual
Bit
7
31:8
Bit
7:0
31:8
Bit
0
1
2
7:3
Symbol
Pad
-
Symbol
Start
Mode
AutoRestart
-
Symbol
Error in RX FIFO
(RXFE)
-
bit description
0x4009 C01C) bit description
0x4009 C020) bit description
14.4.10 UARTn Auto-baud Control Register (U0ACR - 0x4000 C020, U2ACR -
14.4.9 UARTn Scratch Pad Register (U0SCR - 0x4000 C01C, U2SCR -
Description
A readable, writable byte.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value
0
1
0
1
0
1
0x4009 801C U3SCR - 0x4009 C01C)
The UnSCR has no effect on the UARTn operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the UnSCR has occurred.
0x4009 8020, U3ACR - 0x4009 C020)
The UARTn Auto-baud Control Register (UnACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Value Description
0
1
Description
This bit is automatically cleared after auto-baud completion.
Auto-baud stop (auto-baud is not running).
Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
Auto-baud mode select bit.
Mode 0.
Mode 1.
No restart.
Restart in case of time-out (counter restarts at next UARTn Rx falling edge)
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
UnLSR[7] is set when a character with a Rx error such as framing error, parity
error or break interrupt, is loaded into the UnRBR. This bit is cleared when the
UnLSR register is read and there are no subsequent errors in the UARTn FIFO.
UnRBR contains no UARTn RX errors or UnFCR[0]=0.
UARTn RBR contains at least one UARTn RX error.
Reserved, the value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 14: LPC17xx UART0/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0x00
NA
Reset value
0
0
0
0
NA
308 of 840
Reset
Value
0
NA