LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 636

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
32.9 JTAG flash programming interface
UM10360
User manual
32.8.10 IAP Status Codes
32.8.9 Re-invoke ISP
Table 597. Re-invoke ISP
Table 598. IAP Status Codes Summary
Debug tools can write parts of the flash image to the RAM and then execute the IAP call
"Copy RAM to Flash" repeatedly with proper offset.
Command
Input
Return Code
Result
Description
Status
Code
0
1
2
3
4
5
6
7
8
9
10
11
Mnemonic
CMD_SUCCESS
INVALID_COMMAND
SRC_ADDR_ERROR
DST_ADDR_ERROR
SRC_ADDR_NOT_MAPPED
DST_ADDR_NOT_MAPPED
COUNT_ERROR
INVALID_SECTOR
SECTOR_NOT_BLANK
SECTOR_NOT_PREPARED_
FOR_WRITE_OPERATION
COMPARE_ERROR
BUSY
Compare
Command code: 5710
None
None.
This command is used to invoke the boot loader in ISP mode. It maps boot
vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets
TIMER1 and resets the U0FDR (see
used when a valid user program is present in the internal flash memory and the
P2.10 pin is not accessible to force the ISP mode. The command does not disable
the PLL hence it is possible to invoke the boot loader when the part is running off
the PLL. In such case the ISP utility should pass the CCLK (crystal or PLL output
depending on the clock source selection
handshake.
Another option is to disable the PLL and select the IRC as the clock source before
making this IAP call. In this case frequency sent by ISP is ignored and IRC and
PLL are used to generate CCLK = 14.748 MHz.
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
Description
Command is executed successfully.
Invalid command.
Source address is not on a word boundary.
Destination address is not on a correct boundary.
Source address is not mapped in the memory map.
Count value is taken in to consideration where
applicable.
Destination address is not mapped in the memory
map. Count value is taken in to consideration where
applicable.
Byte count is not multiple of 4 or is not a permitted
value.
Sector number is invalid.
Sector is not blank.
Command to prepare sector for write operation was
not executed.
Source and destination data is not same.
Flash programming hardware interface is busy.
Section
Section
14.4.12). This command may be
4.4.1) frequency after auto-baud
UM10360
© NXP B.V. 2010. All rights reserved.
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