LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 654

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.3.4.3 LSL
34.2.3.4.4 ROR
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n
places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the
result to 0. See
You can use he LSL #n operation to multiply the value in the register Rm by 2
is regarded as an unsigned integer or a two’s complement signed integer. Overflow can
occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated
to the last bit shifted out, bit[32-n], of the register Rm. These instructions do not affect the
carry flag when used with LSL #0.
Note
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the
register into the left-hand n bits of the result. See
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
rotation, bit[n-1], of the register Rm.
Note
Fig 142. LSR#3
Fig 143. LSL#3
•
•
•
If n is 33 or more and the carry flag is updated, it is updated to 0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Carry
Flag
31
0
0
31
0
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 2 — 19 August 2010
143.
...
Chapter 34: Appendix: Cortex-M3 user guide
...
Figure
144.
5
4
5
3
UM10360
4
© NXP B.V. 2010. All rights reserved.
2
3
1 0
2
0
n
, if the value
0
1 0
Carry
Flag
0
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