LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 409

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
17.7.5 SPI Test Control Register (SPTCR - 0x4002 0010)
17.7.6 SPI Test Status Register (SPTSR - 0x4002 0014)
In Master mode, this register must be an even number greater than or equal to 8.
Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be
calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the
PCLKSEL0 register contents for PCLK_SPI as described in
In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI
peripheral clock selected in
relevant.
Table 364: SPI Clock Counter Register (S0SPCCR - address 0x4002 000C) bit description
Note that the bits in this register are intended for functional verification only. This register
should not be used for normal operation.
Table 365: SPI Test Control Register (SPTCR - address 0x4002 0010) bit description
Note: The bits in this register are intended for functional verification only. This register
should not be used for normal operation.
This register is a replication of the SPI Status Register. The difference between the
registers is that a read of this register will not start the sequence of events required to
clear these status bits. A write to this register will set an interrupt if the write data for the
respective bit is a 1.
Table 366: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description
Bit
7:0
31:8
Bit
0
7:1
31:8
Bit
2:0
3
4
5
Symbol
Counter
-
Symbol
-
Test
-
Symbol
-
ABRT
MODF
ROVR
All information provided in this document is subject to legal disclaimers.
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
SPI test mode. When 0, the SPI operates normally. When 1, SCK will
always be on, independent of master mode select, and data availability
setting.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Slave abort.
Mode fault.
Read overrun.
Description
SPI0 Clock counter setting.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Section
4.7.3. The content of the S0SPCCR register is not
Section
Chapter 17: LPC17xx SPI
4.7.3.
UM10360
© NXP B.V. 2010. All rights reserved.
409 of 840
Reset
Value
0x00
NA
Reset
Value
NA
0
NA
Reset
Value
NA
0
0
0