LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 44

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Example 2
Assumptions:
Calculations:
M = (F
Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that
need must be addressed first. Potential precise values of F
2 × the 48 MHz USB clock. The 2 × insures that the clock has a 50% duty cycle, which
would not be the case for a division of the PLL output by an odd number.
The possibilities for the F
MHz. The smallest frequency for F
within the PLL0 operating range is 288 MHz (3 × 2 × 48 MHz).
Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So,
M = ((288 × 10
necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23
(N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing F
frequency: 288 × 10
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an F
down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the F
when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is
also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle
needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0
settings for 480 MHz are N = 1 and M = 60.
The PLL output must be further divided in order to produce both the CPU clock and the
USB clock. This is accomplished using separate dividers that are described later in this
chapter. See
•
•
•
The USB interface will be used in the application and will be clocked from PLL0.
The desired CPU rate is 60 MHz.
An external 4 MHz crystal or clock source will be used as the system clock source.
This clock source could be the Internal RC oscillator (IRC).
CCO
× N) / (2 × F
Section 4.7.1
6
All information provided in this document is subject to legal disclaimers.
) × 1) / (2 × (4 × 10
6
/ 60 × 10
Rev. 2 — 19 August 2010
IN
)
CCO
and
rate when the USB is used are 288 MHz, 384 MHz, and 480
6
Section
= 4.8. The nearest integer value for the CPU Clock
6)
CCO
) = 288 / 8 = 36. The result is an integer, which is
Chapter 4: LPC17xx Clocking and power control
that can produce a valid USB clock rate and is
4.7.2.
CCO
rate must be found that can be divided
CCO
CCO
are integer multiples of the
by the desired CPU
UM10360
© NXP B.V. 2010. All rights reserved.
CCO
44 of 840
rate