LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 302

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 273: UARTn Divisor Latch LSB register (U0DLL - address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL -
Table 274: UARTn Divisor Latch MSB register (U0DLM - address 0x4000 C004, U2DLM - 0x4009 8004, U3DLM -
Table 275: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER -
UM10360
User manual
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Bit
0
1
2
7:3
8
Symbol
DLLSB
Symbol
DLMSB
Symbol
RBR Interrupt
Enable
THRE Interrupt
Enable
RX Line Status
Interrupt Enable
-
ABEOIntEn
0x4009 C000 when DLAB = 1) bit description
0x4009 C004 when DLAB = 1) bit description
0x4009 C004 when DLAB = 0) bit description
14.4.4 UARTn Interrupt Enable Register (U0IER - 0x4000 C004, U2IER -
Description
The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the
baud rate of the UARTn.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the
baud rate of the UARTn.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to
select the right value for UnDLL and UnDLM can be found later in this chapter, see
Section
0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0)
The UnIER is used to enable the three UARTn interrupt sources.
Value Description
0
1
0
1
0
1
0
1
14.4.12.
Enables the Receive Data Available interrupt for UARTn. It also controls
the Character Receive Time-out interrupt.
Disable the RDA interrupts.
Enable the RDA interrupts.
Enables the THRE interrupt for UARTn. The status of this can be read
from UnLSR[5].
Disable the THRE interrupts.
Enable the THRE interrupts.
Enables the UARTn RX line status interrupts. The status of this interrupt
can be read from UnLSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Enables the end of auto-baud interrupt.
Disable end of auto-baud Interrupt.
Enable end of auto-baud Interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 14: LPC17xx UART0/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0x01
NA
Reset Value
0x00
NA
Reset Value
0
0
0
NA
0
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