LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 669

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.4.5.1 Syntax
34.2.4.5.2 Operation
34.2.4.5.3 Restrictions
34.2.4.5 LDR, PC-relative
Load register from memory.
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
type is one of:
cond is an optional condition code, see
Rt is the register to load or store.
Rt2 is the second register to load or store.
label is a PC-relative expression. See
LDR loads a register with a value from a PC-relative memory address. The memory
address is specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes
and halfwords can either be signed or unsigned. See
alignment”.
label must be within a limited range of the current instruction.
possible offsets between label and the PC.
Table 618. Offset ranges
Remark: You might have to use the .W suffix to get the maximum offset range. See
Section 34.2.3.8 “Instruction width
In these instructions:
When Rt is PC in a word load instruction:
Instruction type
Word, halfword, signed halfword, byte, signed byte
Two words
•
•
•
B: unsigned byte, zero extend to 32 bits on loads.
SB: signed byte, sign extend to 32 bits (LDR only).
H: unsigned halfword, zero extend to 32 bits on loads.
SH: signed halfword, sign extend to 32 bits (LDR only).
—: omit, for word.
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
; Load two words
selection”.
Section 34.2.3.6 “PC-relative
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.2.3.5 “Address
Offset range
− 4095 to 4095
− 1020 to 1020
Table 618
expressions”.
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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